1. Field of the Invention
Example embodiments of the present invention relate generally to cache memory systems and methods thereof, and more particularly to cache memory systems and methods of retrieving data within the cache memory systems.
2. Description of the Related Art
Generally, an operating speeds of memory (e.g., hard drives, read access memory (RAM), etc.) increase at a slower pace than operating speeds of processors, such as central processing units (CPUs). Thus, there may typically be a difference between the operating speeds of a CPU and a memory used in a memory system. Conventional memory systems may include a cache memory architecture to at least partially account for the above-noted timing discrepancy between memory and processors.
In the conventional cache memory architecture, a CPU may access only a portion of a main memory within a given period of time, and this phenomenon may be referred to as “spatial locality”. A cache memory, having a higher operating speed than the main memory, may be positioned between a CPU and a main memory. The cache memory may store a portion of the main memory (e.g., a most frequently or recently accessed portion). Accordingly, at least some of the time, the cache memory may reduce memory access times. A cache memory may include a plurality of blocks and may perform read and write operations in units of the blocks.
FIG. 1 is a block diagram of a conventional cache memory system 100. Referring to FIG. 1, the conventional cache memory system 100 may include a CPU 110, a cache memory 120 and a main memory 130.
Referring to FIG. 1, if the CPU 110 issues a request for an address ADD in the main memory 130, the cache memory system 100 may determine whether the address ADD is included within the cache memory 120. If the address ADD is determined to be included within the cache memory 120 (e.g., referred to as a “cache hit”), data DATA stored at the address ADD in the cache memory 120 may be transferred to the CPU 110.
However, if the address ADD is determined not to be included within the cache memory 120 (e.g., referred to as a “cache miss”), a block containing the address ADD may be extracted from the main memory 130 and copied to the cache memory 120, and the data DATA stored at the address ADD in the main memory 130 may be transferred to the CPU 110. As used herein, blocks may be units in which data may be written to or read from the cache memory 120 (e.g., 32 bytes, 64 bytes, etc.).
Generally, the larger the block sizes within the cache memory 120, the easier it may be to enhance the spatial locality of the cache memory 120 (e.g., the portion of memory which may be accessed in a given period of time). However, because the storage capacity of the cache memory 120 is relatively limited (e.g., typically much less than the main memory 130), larger block sizes in the cache memory 120 means that a smaller number of blocks are stored within the cache memory 120. Accordingly, if data stored in the cache memory 120 fluctuates frequently, a performance of the cache memory 120 may deteriorate (e.g., a higher probability of misses and a lower probability of hits). Therefore, a block size of a cache memory may typically be fixed (e.g., only one block size per cache), and the block size may be selected to achieve a balance between spatial locality and cache hit/miss performance.
In addition, in the conventional cache memory system 100 of FIG. 1, only one block of data from the main memory 130 may be copied/transferred to the cache memory 120 during any given time. Thus, if the CPU 110 has a spatial locality exceeding a single block size, a probability of obtaining a cache hit of the cache memory 120 may decrease.